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More inquirer drivel. 10.2GHz by 2005 for Intel Nehalem. 0.09u to hit 9.2GHz? Si:Ge?
Quote:
10.20GHz Intel Nehalem slated for 2005
Future Desktop Roadmaps Tejas to reach 9.20GHz, Prescott 5.20GHz
By Mike Magee: ¼ö¿äÀÏ 29 1¿ù 2003, 10:38
IRONY ALERT This story is paid for by INTC.
INCLEMENT WEATHER ON this side of the Atlantic ocean threw a turquoise parakeet off course today and a note it was holding in its beak fell into the INQUIRER's back garden.
The contents of the note appear to reveal future plans for future Intel desktop processors right up until 2005.
By then, according to the note, Intel will be able to deliver 10.20GHz desktop CPUs codenamed "Nehalem" and produced using 65 nanometer technology.
If Intel manages to migrate away from the 90 nanometer technology it will introduce towards the end of this year, by then the "Prescott" core will deliver at least 5.20GHz using the 800MHz system bus.
The immediate successor to Prescott after it tops out at 5.20GHz will be the "Tejas" core, also produced on a 90 nanometer process and delivering 5.60GHz using a 1066MHz system bus. That's slated to start appearing towards the end of 2004.
Tejas will increase in steady increments which appear to be 6GHz, 6.40GHz, 6.80GHz, 7.20GHz, 7.60GHz, 7GHz, 8.40GHz, 8.80GHz and topping out at 9.20GHz.
The first Nehalem is supposed to appear at 9.60GHz before Intel succeeds in its goal to produce a 10GHz+ chip, the Nehalem, and using a 1200MHz front side bus. µ
I actually think this CAN happen. I look at the rate we increased sice the amd-intel cpu wars, and how they are coming up with new materials and techniques. This sounds very plausible to me.
Hopefully AMD will be right along side so as we can still have our toys cheap
I just want to know what is so special about teja's to hit 9.2GHz when Prescott is supposed to start fizzeling around 5.2GHz?
Dual cores on one die making a dual cored 4.6GHz teja's( on die dual prescotts) effectively a 9.2GHz chip? This is where hyperthreading appears to be headed. First it was Hyperthreading. Next with prescott it appears to be dedicated 512k cache for each of the processors(One is a virtual CPU with HT or is it?????).
Prescott is also supposed to have new instructions. Teja's appears to be a more dedicated dual cored CPU unless .09u is really going to ramp to 9.2GHz which is phenominal since .13u seems to be fizzeling in the extreme cases on air around 3.8GHz.
I agree. I don't think that there is ANY precedent for a 9.6 GHz .09 micron chip. Not a P4-based chip anyway.
If Intel is really to meet this goal, they have, I think, three options:
1) Really ramp a 20-stage super piped chip to 9 GHz (even though a similar chip will fizzel at just over HALF that speed).
2) DEEPEN the pipeline (!) Maybe... 35 stage or so. With something like 4 threads moving along at once, it's concievable that being forced into a pipeline dump on ONE of the threads would not hurt performance nearly as much as you might think. Then again, I'm not really sure how this could be done.
3) This stems from the technical article about SMT that was linked here last spring (I've honestly forgotten where it was). The Presocott is supposed to dedicate 1/2 of it's L2 cache to each thread. It's successor could also dupe the L1 and (to some extent) the trace cache. The effect would be an ALMOST double-cored chip. The schedualers and execution units would still be shared. If this were done, and given that the ALU is and always has been 'double pumped' (not that it's ever amounted to jack) on the P4, it might be reasonable to base the chip's 'clockspeed' off of the ALU, L1 and trace caches, rather than the execution units themselves. So what we'd have is a 4600 MHz (external clocked) "9.2" Ghz CPU that performed about 40-60% better than a 4.6 GHz Prescott. Nothing to sneer at, in any case.
My overall reaction to all three possibilities is... YEAH RIGHT! Let's put it this way, Prescott, delayed until Q4, is schedualed for 3.4 GHz this year. Being an optimist, and quite sure that the .09 micron core will scale pretty well, I think they might sneak out a 3.6 or 3.8 GHz chip, especially if AMD is pressuring them with a 4000+.
After that, I expect a VERY fast ramp of the Prescott, because Intel will want to surpass the K8 while it's still limited to a .13 micron proccess. If, as AMD claims, we see a .09 micron proccess release from them in H1 '04 (which I doubt, considering past performance) Intel will have a real race on their hands, and we might see the Prescott stepped and topped off by Q3 at ~5 Ghz.
If that's the case, and the stars are properly allighed, Tejas could make an appearance by the end of the year. But, let's face it, that's one developement schedual Intel will have a tough time keeping.
Worse (for Intel), I don't really know what the K8 can do. I suspect that the .13 micron version will run out of steam at 2.6 GHz (4300+) or maybe 2.8 GHz (4600+). But I could be wrong (SoI did miracles for IBM and MOT, although their chips are very dissimilar from K8). Even then, if AMD has even a reasonably good .09 micron transition, Prescott had better pack an unexpected IPC punch because if it doesn't a 3.4 GHz + K8 isn't even unrealistic, and 3.6 GHz is probably within the realm of possibility, and that's 5500+ or -5800+!!! Pick your poison.
So if Tejas ISN'T ready by the end of 2004, AMD is probably going to be back in the lead (given that Prescott come out and scales soon and fast enough to snatch it).
Then, maybe Intel HAS found the holy grail, and the Tejas will really (truely) go at 9 GHz in one year. But if they've employed "tricks" or changed the way "MHz" are scored the furture gets muddy as hell. Will a 6000+ K8 have similar performance to a 9 GHz Tejas? Only time will tell. Of course, AMD has also babbled about a dual-cored chip, although their approach is topdown rather than bottom up. Would a dual 5000+ rate 9000+? Maybe. Especially when all the software has been optimised for multi-threading (thanks to Intel).
So in the end, this is probably either misleading, and the chips are rated differently or dual cored, or the roadmap is like an AMD roadmap (where time has DIRECTION but no SCALE), and we won't really see it 'til 2007. I can't quite bring myself to believe that Intel is going to REALLY clock a P4 to 9 GHz on a .09 micron proccess, SoI, Strained Si, or otherwise.
Well Hoyle, after all the far fetched speculation and looking into the distant future(which starts to become anyone's guess), I think you summed it up best...
Quote:
So in the end, this is probably either misleading, and the chips are rated differently or dual cored, or the roadmap is like an AMD roadmap (where time has DIRECTION but no SCALE), and we won't really see it 'til 2007. I can't quite bring myself to believe that Intel is going to REALLY clock a P4 to 9 GHz on a .09 micron proccess, SoI, Strained Si, or otherwise.
When we get to .09, that's where things will start to get interesting. Both AMD and Intel have both agreed and publicly stated that at that small of process it starts to become cost effective and economical to fab dual core chips. Clock speed is no longer the future of computing. I mean don't get me wrong, speeds will increase. But the greatest gain in computational power will come from more and more parralism in processing rather than pure speed.
I agree about the increased parralism, but I think that Intel has a much better approach than what AMD is talking about. In Intel's case, they build a very wasteful CPU, then invented a 'virtual' CPU to gain higher efficiency. Of course, right now SMT is lacking REAL parralism, but the improovements they speak of will yield a similar result. Of course, because Intel is working it from the bottom up, they will duplicate exactly and only ehat requires dumplication. AMD is instead talking about just slapping two cores together, which may work, but is more wasteful, it seems to me.
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